The limitations inherent to single signal layer printed circuit boards (PCBs) have led to the development of multilayer PCBs. Such multilayer PCBs may be either single or double-sided and may have multiple signal layers on the surface of and buried within the multilayer PCBs.
While the number of layers that may be provided by a multilayer PCB is theoretically unlimited, problems occur when the number of layers in a multilayer PCB exceeds a reasonable number, particularly when trying to route high-speed electrical signals between electronic components. For example, when making electrical connections between different layers in multilayer PCBs, electrically conductive vias generally are used. While these electrically conductive vias allow direct vertical electrical connections to be made between different layers within a multilayer PCB, there are intrinsic parasitics associated with these electrically conductive vias that can adversely affect the performance of signals propagating therethrough. That is, these electrically conductive vias have intrinsic parasitic resistance, capacitance, and inductance which can adversely affect signals propagating along each electrically conductive via. In addition, these intrinsic parasitics can also have an adverse effect on the manufacturability of a PCB and thus the cost thereof. Because of their adverse affect on signal performance, these intrinsic parasitics can also limit the bandwidth of signals propagating along each electrically conductive via. These adverse affects only increase as the number of layers in a multilayer PCB increase.
Due to the adverse effects on signal integrity as the layer count of a PCB increase, techniques have been developed to provide for “channel routing” within a PCB to reduce the number of layers necessary to provide the requisite electrical connections. An exemplary channel routing technique is described in U.S. Pat. No. 6,388,890 issued on May 14, 2002 to Kwong et al., the entirety of which is hereby incorporated by reference herein. Kwong et al. disclose a technique for manufacturing and using a PCB wherein certain vias extend only through a subset of the layers of the PCB to create channels in the portions of the PCB where vias are absent. These channels then may be used to route a larger number of signal, power, ground and/or test traces between vias thereby reducing the number of layers necessary to provide a certain number of electrical connections.
While reducing the requisite number of signal layers, conventional channel routing techniques typically are limited to surface mount devices (SMDs), e.g., ball grid array (BGA) packages. Through hole-based devices (THDs), such as pin grid array (PGA) packages, generally have pins of a pre-determined length that may be incompatible with the reduced-depth vias used in PCBs having channel routing. As a result, THDs and other devices having pins of a uniform length often cannot be utilized in channel-routed PCBs and therefore are utilized with other types of PCBs that require a greater number of signal layers. This increased number of requisite signal layers may then create or magnify the adverse signal effects caused by an increased number of layers, as described above.
In view of the foregoing, it would be desirable to provide a technique for implementing a THD and other pin-based packages in a multilayer channel routed PCB.